The present invention relates to integrated circuit structures and fabrication methods, and more particularly to wafer level yield analysis.
The economics of modern integrated circuit microfabrication are unusual. Every integrated circuit is tested at the end of manufacturing process, and a significant fraction of the integrated circuits must be discarded. (Typical yield loss may be a few percent to several tens of percent). Since the maximum number of wafers which can be processed per hour by the very expensive capital equipment is nearly fixed, the yield of good devices per wafer is a key determinant of profitability. This means that any improvement in yield is of great interest.
One of the key elements in yield optimization is fault analysis. Since there are numerous processing steps and machines which can cause yield loss, it is not necessarily obvious which processes are performing optimally and which are not. Test structures can indicate physical conditions, such as shorts, opens, degraded sheet resistance, or degraded contact resistance, but it still may not be apparent what, in the processing conditions, is leading to these physical conditions in the resulting structure. It is also very difficult to detect cooperative effects, where two processes are both out of tune in a way which combines with disastrous synergy.
An important recent innovation in fault analysis has been wafer randomization. Wafers are usually routed through a fab in lots of e.g. 25, and some fault analysis information can be derived from studying variation over time, or from lot-to-lot comparisons; but when the order of wafers within a lot remained fixed (as was formerly traditional), the information which could be derived from intralot comparison was minimal. For example, it was easy to observe (for example) that failure rates increased in the last half of a lot, but difficult to infer which machine might have been the source of this trend. However, by shuffling the order of wafers before critical processing steps, vastly more information could be derived from fault correlation analysis. (Mathematically, n wafer randomizations in a lot of k wafers allows multidimensional correlation and filtering operations, using an n+1-dimensional sequence vector.)
In order to take advantage of the fault correlation potential of wafer randomization, the wafer sequence data for each processing step must be retained. The simplest way to do this is by automatically validating the identity of every wafer before critical processing steps, and recording the resulting data. This provides the data for the sequence vector, and has the side benefit of preventing wafer mix-ups and potential misprocess scrap of mixed lots.
Also, since the spatial position of each wafer is consistently fixed at critical steps (since the machines normally reference the wafer notches or flats), fault analysis can (and should) also correlate trends to spatial locations on the wafer.
The input to this improved correlation capability is not limited to failures. Parametric data (e.g. from probe or device performance testing) can also be correlated back into the different stages in the process, to permit further optimization of yield (and optionally also performance).
A benefit of this is improved engineering productivity: process engineers can focus on leads from correlation analysis, instead of having to guess which step or combination of steps may be out of tune. The result is quicker and more efficient detection of lot yield problems. (A different way to think of this is that every production lot can also be analyzed as an experimental lot, WITHOUT any loss of yield or of production throughput.)
The original form Wafer Sleuth technology from Texas Instruments, used in combination with randomizer stations for wafer shuffling, provides many of these benefits. The present application implements further improvements in fault correlation, and in associated production steps.
In-Situ Randomization and Recording of Wafer Processing Order at Process Tool
The present application discloses an innovative way to randomize wafers in-situ during processing. The preferred embodiment is used with tools that have wafer pick and place capability, meaning they can select any wafer from a cassette rather than just accessing them in a particular order. Randomization of wafer order is provided by randomly pulling wafers from any slot on the send (incoming) cassette, or replacing wafers to a random slot in the receive (outgoing) cassette. Further randomization can be obtained by combining these methods.
In another embodiment, which uses a wafer tool with pick and place capability, wafers are completely randomized at the load and/or unlead stations prior to, or after, processing. This method requires there be at least one empty slot for a wafer, or another wafer staging area available. This method is best used in a process where the time delay does not affect throughput, such as when the randomization is done while other wafers are occupying the needed tool.
In yet another embodiment, which applies to tools without pick and place capability, and for lot sizes of less than 25 (or the maximum number of wafer slots in the cassette holder, meaning free slots exist in the holder), wafers use a second temporary holding area, and wafers are pulled directly from the send cassette and either randomly stored or sent to processing. Wafers can then be pulled for processing randomly either from the next slot in the send cassette, or form the staging area. Wafers can also, at the receive end after processing, be randomly placed in the cassette or in a staging area, and wafers thereafter can be returned to the receive cassette either from the process tool or from the holding area.
In order to keep track of wafer processing order, the wafer number, or wafer ID, is read inside each processing tool. In the case of a multiple process chamber tool, the wafer number or ID is read at each process chamber. Note that both wafer ID and wafer order are tracked in the preferred embodiments. The resulting information about the sequence of wafers through each critical processing step can then be used for fault correlation.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
prevents wafer mix-up from ex-situ shuffling;
reduces manufacturing time by eliminating separate randomization step;
saves fab floor space used for randomizers.